Title of Invention

"AN IMPROVED MULTI-STAGE BINARY HIERARCHY DECODER"

Abstract

This invention relates to an improved multi-stage binary hierarchy decoder comprising at least one of the decoding stages subsequent to the first stage implemented as a transmission gate matrix in which a single CMOS transmission gate, having a control node and an input node, each of which is directly coupled to respective first stage output nodes that enables an active input from the previous stage to its output, thereby resulting in reduced area requirements when implemented as an integrated circuit.

Full Text

Field of the invention The present invention relates to an improved multistage binary hierarchy decoder for large number of outputs using smaller size decoders and a pass gate matrix. Background of the invention Fig.l shows an example of a 2x4 decoder with active low outputs. The decoder has two inputs (1.1) and (1.2) and 4 outputs (1.3) to (1.6). Figure 2 defines another implementation of 2x4 decoder, which has active high outputs. The 2 inputs are (2.1) and (2.2) while the outputs are (2.3) to (2.6). These decoders are examples of flat decoders. However, this approach is not suitable for larger decoders, as it requires substantial hardware. In such cases multi-stage decoders are used to reduce the hardware required. As an example, a 4x16 decoder can be made using two 2x4 decoders. There are several schemes for two stage decoding. One such scheme is shown in fig 3. Here two decoders of the type shown in figl are used as first stage of the decoder with inputs (3.1) and (3.2) for the first decoder and inputs (3.3) and (3.4) for the second decoder. In the second stage of the decoder each output from each 2x4 decoder is NORed with each corresponding output of the second 2x4 decoder forming a 4x16 decoder with outputs OUTΦ through OUT15. This decoder works as active high output. For making a decoder with active low outputs, decoder of fig 2 can be used as the first stage of decoder and in the second stage each output of the first 2x4 decoder will be NANDed with each corresponding output of the second 2x4 decoder to form the 4x16 decoder. Even such two stage decoder schemes consume a lot of hardware and are hence not suitable for making very large size decoders. The object and summary of the invention Accordingly, the object of the present invention is to provide an apparatus and method for overcoming the above drawbacks for making large size decoders by using a binary hierarchy of smaller size decoders together with a pass gate matrix. To achieve the said objective, the present invention provides an improved multistage binary hierarchy decoder comprising at least one of the decoding stages subsequent to the first stage implemented as a transmission gate matrix in which a single CMOS transmission gate, having a control node and an input node, each of which is directly coupled to respective first stage output nodes that enables an active input from the previous stage to its output, thereby resulting in reduced area requirements when implemented as an integrated circuit. The said transmission gate matrix is an arrangement of transmission gates in row and column form with the gates of all transmission gates in the same column connected together to a single output from a first decoder from the previous stage, while the inputs of all transmission gates in the same row are connected together to a single output of the second decoder from the previous stage. A discharge matrix is provided at the output of said transmission gate matrix for the case when the outputs are active high in order to pull inactive outputs low. A charge matrix is provided at the output of said transmission gate matrix for the case of active low outputs in order to pull inactive outputs high. The said discharge matrix is an arrangement of grouped NMOS transistors having source terminals connected to ground, gate terminals of each group connected to a corresponding input from a decoder of the previous stage that is used to drive gate terminals of transmission gates in said transmission gate matrix and each drain connected to an output from said transmission gate matrix. The said charge matrix is an arrangement of grouped PMOS transistors having source terminals connected to the positive supply terminal, gate terminals of each group connected to a corresponding input from a decoder of the previous stage that is used to drive gate terminals of transmission gates in said transmission gate matrix, and each drain connected to an output from said transmission gate matrix. An improved multi-stage binary hierarchy decoder comprises: • a first input stage operable to receive a first portion of a binary; code and having a plurality of output nodes; • a second input stage operable to receive a second portion of the binary code and having a plurality of output nodes; • a third input stage operable to receive a third portion of the binary code and having a plurality of output nodes; • a fourth input stage operable to receive a fourth portion of the binary code and having a plurality of output nodes; • a first transmission gate matrix coupled to the output nodes of the first and second stages and having a plurality of CMOS transmission gates, each gate having a control node directly coupled to a respective one of the first input stage output nodes, an input node directly coupled to a respective one of the second input stage output nodes, and an output node that corresponds to a respective value of a combination of the first and second portions of the binary code; • a second transmission gate matrix coupled to the output nodes of the third and fourth stages and having a plurality of CMOS transmission gates, each gate having a control node directly coupled to a respective one of the third input stage output nodes, an input node directly coupled to a respective one of the fourth input stage output nodes, and an output node that corresponds to a respective value of a combination of the third and fourth portions of the binary code; and • a third transmission gate matrix coupled to the transmission gates of the first and second transmission gate matrices and having a plurality of transmission gates that each correspond to a respective value of the binary code. An improved multi-stage binary hierarchy decoder, wherein: • the first input stage comprises two input nodes and four output nodes; ^ • the second input stage comprises two input nodes and four output nodes; • the third input stage comprises three input nodes and eight output nodes; and • the fourth input stage comprises three input nodes and eight output nodes. Brief description of the drawings: The invention will now be described with reference to the accompanying drawings Figure 1 shows a design of 2x4 decoder with active low outputs using NAND gates. Figure 2 shows a design of 2x4 decoder with active high outputs using NOR gates. Figure 3 shows a conventional 2-stage 4x16 decoder. Figure 4 shows the block diagram of the proposed scheme. Figure 5 shows the pass gate array used for implementing the decoder design. Figure 6 shows the discharge transistor matrix. Figure 7 shows the charging transistor matrix in case of a decoder with active low outputs. Figure 8 shows an example of a 10x1024 decoder using a hierarchical decoding structure in conventional technology Figure 9 shows the 10x1024 decoder based on a hierarchical decoding structure according to this invention. Detailed description of the invention Figures 1, 2 & 3 have been described in the background of the invention. Fig 4 shows the block diagram of a preferred embodiment of this invention for an example of a 4 x 16 decoder using two 2x4 decoders. A pass gate array is used as a cross-connect for the two decoders. One of the two stage -1 decoders (4.1) provides active low outputs which are connected to the 4 horizontal input lines HO to H3 of the Transmission Gate Matrix (4.3). The other stage-1 decoder (4.2) provides active high outputs that are connected to the 4 vertical input lines VO+0 V3 of the Transmission Gate Matrix (4.3). The combination of horizontal and Vertical inputs is used to select one of the Transmission Gates (located at the intersection of the active horizontal and vertical inputs) inside the Transmission Gate Matrix (4.3) and provide an active high output on one of the 16 output lines WRO to WR 15. A Discharge transistors Matrix (4.4) controlled by the 4 outputs from decoder (4.1) is used to pull-down the inactive Transmission Gate Matrix outputs to a well-defined inactive low level. Figure 5 shows the internal structure of the Transmission Gate Matrix. For the instant example of 4x6 decoder the 4 outputs from the first 2x4 decoder are applied to the horizontal input lines (HO-H3) while the 4 outputs from the other 2x4 decoder are applied to the vertical inputs (VO-V3). The first 2x4 decoder has active low outputs while the second 2x4 decoder has active high outputs. Depending on the input bit pattern one output line of the horizontal decoder will go low and others will be high and one output line of the vertical decoder will be high while the others will be low. The gates of the Transmission Gate in each column of the matrix (301) to (304), (305) to (308), (309) to (312) and (313) to (316) are connected with the output signals and the compliment of the output signals from the horizontal decoder. The inputs of the Transmission Gates in each row of the matrix are joined together and the vertical decoder. So the inputs of transmission gates (301), (305), (309) and (313) are joined and connected to the first output of the vertical decoder, (302), (306), (310) and (314) to the second output (303), (307), (311) and (315) to the third output and (304), (308), (312) and (316) to the final output. For an input sequence of 0000 the HO output will go low and VO output will go high. Since only the HO output of the horizontal decoder is low, pass gates 301- 304 will be ON. Also since only VO output of the vertical decoder is high, the input of pass-gates 301, 305, 309 and 313 will be at logic high. Pass gates 305, 309 and 313 are OFF so only gate 301 (which is at the cross-point of the HO and VO) will pass logic high to its output. In other words, output 'wrO' will be active high. If the input sequence changes to 0001 then again HO line will be low but now VI line go high and gate 302 (cross-point of VI and HO) will pass a high so this time only 'wrl' will go active high. Similarly, if the input sequences changes to 0101 then HI will go low and VI will go high. This time pass-gates 305 to 308 will be ON and logic high will be at the input of 302, 306, 310 and 314. Only pass-gate 306 (cross-point of the VI and HI) will provide an output high setting output line 'wr5' high. The outputs of the transmission gates that are OFF need to be provided a defined level as these would be otherwise 'floating' at undefined levels. A Discharge Matrix provides a solution. Figure 6 shows the structure a preferred implementation of the Discharge Matrix. The output lines of the Transmission Gate Matrix 'wrO' to 'wr!5' are connected to the drains of individual NMOS transistors in the Discharge Matrix (210) to (213), (220) to (223), (230) to (233) and (240) to (243). The gates of NMOS transistors (210-213) are joined together and connected to HO horizontal outputs, NMOS, (220-223) gates are connected to HI, NMOS (230-233) gates are connected to H2 and NMOS (240-243) gates are connected to H3. The source of all the NMOS transistors is connected to the ground. Since the horizontal decoder provides active low outputs only one row of NMOS transistor (those connected to the active horizontal signal) will be OFF while the others will be ON at any time. The ON NMOS transistors will hold the output lines of the OFF Transmission Gates of the Transmission Gate Matrix at logic 0. When the input sequence is at 0001, HO is low and rest are high. At this time NMOS (210-213) are OFF and rest are ON. So output line 'wr4-wr!5' are pulled low. If now the input sequence changes to the 0101 then HO will go high and previously high 'wrl' line will discharge through NMOS (211). At this time HI line will be low and NMOS (220-223) will be OFF. For the case of a decoder with active low outputs, the Horizontal decoder needs to be made an active high output type, the vertical decoder an active low output type and the Discharge Matrix needs to be replaced by a Charge Matrix. Figure 7 shows a diagram of a preferred embodiment of a Charge Matrix. The Charge Matrix is very similar to the Discharge Matrix with the NMOS transistors replaced by PMOS transistors having sources connected to the positive supply. Again only one row of the PMOS transistors will be OFF and rest will be ON, which will pull outputs connected to them high. And the outputs, which are connected to an OFF PMOS row will reflect the value of vertical decoder output (this particular column will be ON in pass gate array). Since only one output of vertical decoder will be low in this configuration, only one output (which will be at the cross point of low output of vertical decoder and low output of horizontal decoder) will go low of the final decoder and rest will be high. Figure 8 shows an example of a large 10x1024 decoder using conventional technology. The hierarchical structure us a 3-stage design using a combination of 3x8 decoders (8.1) and (8.2), and 2x4 decoders (8.3) and (8.4) in the first stage, connected to two 5x32 decoders (8.5) and (8.6) in the second stage and a 10x1024 decoder (8.7) in the final stage. Figure 9 shows one of the possible implementation of a 10x1024 decoder according to this invention. The first stage comprises two 3x8 decoders (9.1) and (9.2) and two 2x4 decoders (9.3) and (9.4). The two 3x8 decoders connect to a 6x64 Transmission Gate Matrix (9.6) with associated Charge Matrix / Discharge Matrix (not shown) while the two 2x4 decoders connect to a 4x16 Transmission Gate Matrix (9.5) with associated Charge Matrix / Discharge Matrix (not shown). In the final stage the outputs from the 6x64 Transmission Gate Matrix (9.6) and 4x16 Transmission Gate Matrix (9.5) are connected to a 10x1024 Transmission Gate Matrix (9.8) with associated Charge matrix / Discharge Matrix (not shown). We claim: 1. An improved multi-stage binary hierarchy decoder comprising at least one of the decoding stages subsequent to the first stage implemented as a transmission gate matrix in which a single CMOS transmission gate, having a control node and an input node, each of which is directly coupled to respective first stage output nodes that enables an active input from the previous stage to its output, thereby resulting in reduced area requirements when implemented as an integrated circuit. 2. An improved multi-stage binary hierarchy decoder as claimed in claim 1, wherein said transmission gate matrix is an arrangement of transmission gates in row and column form with the gates of all transmission gates in the same column connected together to a single output from a first decoder from the previous stage, while the inputs of all transmission gates in the same row are connected together to a single output of the second decoder from the previous stage. 3. An improved multi-stage binary hierarchy decoder as claimed in claim 1, wherein a discharge matrix is provided at the output of said transmission gate matrix for the case when the outputs are active high in order to pull inactive outputs low. 4. An improved multi-stage binary hierarchy decoder as claimed in claim 1, wherein a charge matrix is provided at the output of said transmission gate matrix for the case of active low outputs in order to pull inactive outputs high. 5. An improved multi-stage binary hierarchy decoder as claimed in claim 3, wherein said discharge matrix is an arrangement of grouped NMOS transistors having source terminals connected to ground, gate terminals of each group connected to a corresponding input from a decoder of the previous stage that is used to drive gate terminals of transmission gates in said transmission gate matrix and each drain connected to an output from said transmission gate matrix. 6. An improved multi-stage binary hierarchy decoder as claimed in claim 4 wherein said charge matrix is an arrangement of grouped PMOS transistors having source terminals connected to the positive supply terminal, gate terminals of each group connected to a corresponding input from a decoder of the previous stage that is used to drive gate terminals of transmission gates in said transmission gate matrix, and each drain connected to an output from said transmission gate matrix. 7. An improved multi-stage binary hierarchy decoder comprising: • a first input stage operable to receive a first portion of a binary code and having a plurality of output nodes; • a second input stage operable to receive a second portion of the binary code and having a plurality of output nodes; • a third input stage operable to receive a third portion of the binary code and having a plurality of output nodes; • a fourth input stage operable to receive a fourth portion of the binary code and having a plurality of output nodes; • a first transmission gate matrix coupled to the output nodes of the first and second stages and having a plurality of CMOS transmission gates, each gate having a control node directly coupled to a respective one of the first input stage output nodes, an input node directly coupled to a respective one of the second input stage output nodes, and an output node that corresponds to a respective value of a combination of the first and second portions of the binary code; • a second transmission gate matrix coupled to the output nodes of the third and fourth stages and having a plurality of CMOS transmission gates, each gate having a control node directly coupled to a respective one of the third input stage output nodes, an input node directly coupled to a respective one of the fourth input stage output nodes, and an output node that corresponds to a respective value of a combination of the third and fourth portions of the binary code; and • a third transmission gate matrix coupled to the transmission gates of the first and second transmission gate matrices and having a plurality of transmission gates that each correspond to a respective value of the binary code. 8. An improved multi-stage binary hierarchy decoder as claimed in claim 7, wherein: • the first input stage comprises two input nodes and four output nodes; • the second input stage comprises two input nodes and four output nodes; • the third input stage comprises three input nodes and eight output nodes; and • the fourth input stage comprises three input nodes and eight output nodes. 9. An improved multi-stage binary hierarchy decoder substantially as herein described with reference to and as illustrated in figures 4 to 9 of the accompanying drawings. r

Documents:

1040-del-2001-abstract.pdf

1040-del-2001-claims.pdf

1040-del-2001-correspondence-others.pdf

1040-del-2001-correspondence-po.pdf

1040-del-2001-description (complete).pdf

1040-del-2001-drawings.pdf

1040-del-2001-form-1.pdf

1040-del-2001-form-13.pdf

1040-del-2001-form-18.pdf

1040-del-2001-form-2.pdf

1040-del-2001-form-3.pdf

1040-del-2001-pa.pdf

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