Title of Invention	POWER BACKUP PROCESSOR
Abstract	The present invention concerns a power backup processor unit 200 comprising a first AC input line 313 provided to be connected to an AC power supply; first and second AC output lines 315, 316 provided to be connected to a critical load 204, wherein the first AC output line 315; and a neutral line 314 provided to be connected to a neutral port. The power backup processor unit 200 also comprises first and second DC voltage busses 311,312 provided to be connected to a DC power supply 206; and a capacitor 207 as well as first, second and third half-bridge circuits 301,302,303 interposed between the first and second DC voltage busses 311,312. To said first and second DC voltage busses 311,312 the first half-bridge circuit 301 links the first AC input line 313, the second half-bridge circuit 302 the first AC output line 315 and the third half-bridge circuit 303 the neutral line 314. A series of controllers 208 is provided to command the first and second half-bridge circuits 301,302 using pulse width modulation to convert an input AC voltage into two different, substantially continuous voltages at the first and the second DC voltage busses 311,312 and these into an output AC voltage at the first AC output line 315. The controllers 208 are also provided to command the third half-bridge circuit 303 so as to generate an output voltage at the second AC output line 316 that runs countercyclically to that of the first AC output line 315, thus achieving an increased voltage between the two AC output lines 315,316. The invention also concerns a method of controlling said power backup processor unit 200. Figure 3.

Title of Invention

POWER BACKUP PROCESSOR

Abstract

The present invention concerns a power backup processor unit 200 comprising a first AC input line 313 provided to be connected to an AC power supply; first and second AC output lines 315, 316 provided to be connected to a critical load 204, wherein the first AC output line 315; and a neutral line 314 provided to be connected to a neutral port. The power backup processor unit 200 also comprises first and second DC voltage busses 311,312 provided to be connected to a DC power supply 206; and a capacitor 207 as well as first, second and third half-bridge circuits 301,302,303 interposed between the first and second DC voltage busses 311,312. To said first and second DC voltage busses 311,312 the first half-bridge circuit 301 links the first AC input line 313, the second half-bridge circuit 302 the first AC output line 315 and the third half-bridge circuit 303 the neutral line 314. A series of controllers 208 is provided to command the first and second half-bridge circuits 301,302 using pulse width modulation to convert an input AC voltage into two different, substantially continuous voltages at the first and the second DC voltage busses 311,312 and these into an output AC voltage at the first AC output line 315. The controllers 208 are also provided to command the third half-bridge circuit 303 so as to generate an output voltage at the second AC output line 316 that runs countercyclically to that of the first AC output line 315, thus achieving an increased voltage between the two AC output lines 315,316. The invention also concerns a method of controlling said power backup processor unit 200. Figure 3.

Full Text	"Power backup processor" The present invention relates to a power backup processor unit comprising a first AC input line comprising a first inductance and provided to be connected to an AC power supply, a first AC output line comprising a second inductance and provided to be connected to a critical load, a second AC output line provided to be connected to the critical load, a neutral line provided to be connected to a neutral port, first and second DC voltage busses provided to be connected to a DC power supply, a capacitor interposed between the first and second DC voltage busses, a first half-bridge circuit comprising first and second switches, wherein the first switch is connected between the first AC input line and the first DC voltage bus and the second switch is connected between the first AC input line and the second DC voltage bus, a second half-bridge circuit comprising third and fourth switches, wherein the third switch is connected between the first AC output line and the first DC voltage bus and the fourth switch is connected between the first AC output line and the second DC voltage bus, a third half-bridge circuit comprising fifth and sixth switches, wherein the fifth switch is connected between the neutral line and the first DC voltage bus and the sixth switch i is connected between the neutral line and the second DC voltage bus. The processor further comprises a series of controllers provided to command the switches, wherein said series of controllers is provided to command at least the first to fourth switches using pulse width modulation. The present invention also relates to a method of operating said power backup processor. Power backup processors are typically used in the telecommunication industry to ensure continuous delivery of AC energy to critical applications such as a central office of a telecommunication operator. A configuration typically known from the state of the art and comprising a series of converters is illustrated in Figure 1. In this configuration, a first converter 101, which is an AC/DC converter, has a first AC input and a first DC output. The first AC input comprises a first AC input line 119 and a neutral line 120. Said first AC input line 119 is provided to be connected to a single-phase AC power supply, whereas said neutral line 120 is provided to be connected to a neutral port. A second converter 102, which is a DC/AC converter, has a first DC input and a first AC output, which comprises a first AC output line 121 and a second neutral line 122. Said first AC output line 121 is provided to be connected to a critical load 108, whereas said second neutral line 122 is provided to be connected to a neutral. A third converter 103, which is a DC/DC converter, has a second DC input and a second DC output, said second DC input being provided to be connected to a DC power supply. A fourth converter 104, which is another DC/DC converter, has a third DC input and a third DC output. The first DC output is connected to the third DC input, the third DC output to the second DC input and the second DC output to the first DC input. The second converter 102 connected to the third converter 103 form together an inverter 100b, and the first converter 101 connected to the fourth converter 104 form together a rectifier 100a. A battery 106 is typically used as a DC power supply and therefore connected between the output from the rectifier 100a and the input from the inverter 100b. A switching unit 105 comprising switches 105a and 105b and a micro-controller 105c to control the switches is foreseen to i allow to switch between a connection using the power processor formed by the rectifier 100a and inverter 100b and a connection through the cable 107. The critical load 108 is here illustrated by one resistance. In practise, the critical load may be formed by a plurality of units connected in parallel to the processor. A problem with this known configuration as illustrated in Figure 1 is that the efficiency is relatively low. From the single-phase AC power supply to the critical load, the current needs to pass through four converters and one switch. The efficiency obtained through such a circuit is typically around 80%. When the critical load is fed with the DC power supply, the current needs to pass through two converters and one switch yielding an efficiency in the order of 90%. United States Patent 4,709,318 discloses an alternative configuration which comprises just three converters, these three converters being a first converter, which is an AC/DC converter with a first AC input and a first DC output, a second converter, which is a DC/AC converter with a first DC input and a first AC output, and a third converter, which is a DC/DC converter provided with a second DC input and a second DC output. In this alternative configuration of the state of the art, the first AC input is provided to be connected to an AC power source, the first AC output is provided to be connected to a critical load, the second DC input is provided to be connected to a DC power source and both the first and second DC outputs are connected to two DC voltage busses in turn connected to the first DC input. With this configuration, the current only needs to pass through two converters between the AC power supply and the critical load. However, in this disclosure the first and second converters are such that the voltage between the DC voltage busses is comparatively high, namely 400 V DC to achieve a 120 V RMS AC output voltage. Such high voltage requires dimensioning the elements of the converters accordingly, increasing the cost while reducing both efficiency and reliability. United States Patent Application Publication US 2005/0162137 A1 discloses a power backup processor comprising the features of the preambles of the independent claims. In particular, this power backup processor comprises three AC phase input lines, each comprising an inductance and provided to be connected to a three-phase AC power supply, three AC phase output lines, each comprising another inductance and provided to be connected to a critical load, a first neutral line, first and second DC voltage busses provided to be connected to a DC power supply, a capacitor interposed between the first and second DC voltage busses, and a half-bridge circuit for each one of the three AC phase input lines, three AC phase output lines and first neutral line. Each half-bridge circuit comprises a switch connected between the corresponding AC phase input, AG phase output or neutral line and the first DC voltage bus and another switch connected between the same corresponding AC phase input, AC phase output or neutral line and the second DC voltage bus. This configuration also comprises a series of controllers provided to command all switches using pulse width modulation. In operation, the half-bridge circuits corresponding to the three AC phase input lines are commanded using pulse width modulation so as to generate, from the three-phase AC input, a nearly continuous positive voltage at the first DC voltage bus and a nearly continuous i negative voltage at the second DC voltage bus. The half-bridge circuit corresponding to the first neutral line is commanded merely to compensate minor voltage fluctuations at the first and second DC voltage busses, both switches of this half-bridge being closed only for a very small percentage of the time and in very short pulses. The first neutral 5 line in this configuration therefore operates merely as a "0" volts axis. The normal object of this device is the zero sequence generation to reduce harmonic voltages on a three-phase output. These configuration and control method, apart from being suitable only for three-phase AC power supplies, furthermore also require a comparatively high DC ) voltage between the first and second DC voltage busses, namely up to 862 V DC for an output line-to-neutral voltage of 277 V. It is a primary object of the present invention to provide a power backup processor and a method of operating said power backup processor suitable for a single-phase AC power supply and with a higher efficiency, at least when the critical load is fed with the single-phase AC power supply, while having a high availability and quality of voltage supply, and avoiding the drawbacks related to high DC voltages. To this end, the power backup processor unit further comprises a fourth half-bridge circuit comprising seventh and eighth switches, wherein the seventh switch is connected between the second AC output line and the first DC voltage bus and the eighth switch is connected between the second AC output line and the second DC voltage bus, the series of controllers being provided to open the fifth switch and close the sixth switch for a period t1 of at least 50%, and preferably at least 95%, of a first half of a cycle of Vl in and close the fifth switch and open the sixth switch for a period t2 of at least 50%, and preferably at least 95%, of a second half of said cycle of VL,in- Preferably, said series of controllers is also provided to open the seventh switch and close the eighth switch for a period V of at least 50%, and preferably at least 95%, of a first half of a cycle of VL,0Ut and close the third switch and open the fourth switch for a period t2' of at least 50%, and preferably at least 95% of a second half of said cycle of VLout. This arrangement generates a voltage VN,out at the second AC output line that runs countercyclical^ to VL,0Ut. As a result, the voltage VLoad between the two connections to the load has an amplitude that is the sum of those of VLout and VNf0ut- An efficiency in the order of 90% can be obtained with the AC power supply. In addition, this circuitry has fewer components and is hence simplified when comparing it with prior art circuitries. A further consequence is that it allows having simultaneously a sinusoidal input current (without harmonics) while having a non linear critical load at the i output supplied by a sinusoidal voltage with a non sinusoidal current (with current harmonics). This insures proper harmonic filtering of the AC input voltage and simultaneously the AC output current. It further allows proper functioning when a small phase shift between input (AC power supply) and output (at the critical load) is present as well as in case small voltage differences between input and output occur. Alternatively, the neutral line is provided to be directly connected to the second AC output line, and the power backup processor further comprises a third inductance connected between the neutral line and the third half-bridge circuit, the series of controllers being provided to open the fifth switch and close the sixth switch for a period ti of at least 50%, and preferably at least 95%, of a first half of a cycle of VLiin and close the fifth switch and open the sixth switch for a period t2 of at least 50%, and preferably at least 95%, of a second half of said cycle of VL,jrv This second embodiment also generates a VN,0Ut that is countercyclical to VL,out- While in this simpler arrangement it is not possible to change the frequency and phase displacement of VL,0Ut with respect to VLin, the reduction in the number of components further increases the reliability, as well as the efficiency, which can reach around 95%. Advantageously, the fifth and sixth switches and/or the seventh and eight switches are pulse-width moderated during a period t3, respectively t3', between U and t2, respectively V and t2\ so that VN,0Ut presents a continuity of at least its first and second derivates. This improves the longevity of the components and the cleanliness of the output. i Preferably, the series of controllers consists of one controller unit. As opposed to individual controllers for each converter, this allows managing more efficiently and easily the energy flow, without the need of adding additional components to manage communication between individual controllers. ) Preferably, the power backup processor unit further comprises a DC/DC converter connected to the first and second DC voltage busses for connecting said first and second DC voltage busses to said DC power source. This allows the use of a DC power source with a different, usually lower, voltage than the voltage between the two DC voltage busses. In a particular embodiment, the DC/DC converter is bi directional. This makes it possible to use the device according to the invention as a rectifier, wherein current would flow from the AC input to the DC power source for recharging. Advantageously, the first, second, fifth and sixth switches are power bi-directional and the series of controllers is provided to run the first half-bridge circuit in reverse, so as to convert a DC voltage between the two DC voltage busses into an AC voltage at the first AC input line. This allows using the device according to the invention as a means to supply energy from the DC power input into the AC power supply. A current flow in this direction could be applied for example in photovoltaic cell applications, wherein the energy generated by the cells is fed back to the AC power supply when not used by the critical load. It can further be advantageous if the third, fourth and, if provided, the seventh and eighth switches are power bi-directional, and the series of controllers is also provided to run the second half-bridge circuit in reverse, so as to convert an AC voltage between the first and second AC output lines into a DC voltage between the two DC voltage busses. This allows the recuperation of energy from the critical load back into the AC and/or DC power supply, which principle could be applied to elevator systems. Preferably, the power backup processor according to the invention comprises a plurality of power backup processor units connected in parallel, each power backup processor unit comprising the first, second and third converters as claimed in any one of the preceding claims. This allows to guarantee continuous operation should one of the units fail to operate and without the presence of a single point or failure element such as switch 105a in the prior art device of Figure 1. The device according to particular embodiments of the invention allows to suppress the following two negative effects occurring simultaneously and present in the prior art devices as illustrated in Figure 1. First, when power is supplied through switch 105b and cable 107, disturbances can occur by supplying power to the critical load without filtering. Secondly, when a critical non linear load is supplied, harmonic currents are generated on the AC power supply. This can lead to deterioration of the quality of the AC power supply voltage caused by harmonic currents which are applied to the AC power supply. Other details and advantages will appear from the description of the annexed drawings. Figure 1 illustrates a typical configuration of a power backup processor according to the prior art. Figure 2 illustrates a first embodiment of the power backup processor unit according to the invention. Figure 3 illustrates part of said first embodiment of the power backup processor unit according to the invention. Figure 4 illustrates voltage conversion using pulse width modulation. Figure 5 illustrates an example of the output voltages of the power backup processor unit according to the invention. Figure 6 illustrates another example of the output voltages of the power backup processor unit according to the invention. Figure 7 illustrates a second embodiment of the power backup processor according to the invention. Figure 8 illustrates part of said second embodiment of the power backup processor according to the invention. Figure 9 illustrates a further embodiment of the power backup processor according to the invention with several units in parallel. In a first embodiment of the invention, as illustrated in Figure 2, a power processor unit 200 comprises a first converter 201 comprising an AC input connected to an AC power supply 205. This converter is provided to convert AC power at for example 230 V AC RMS to a DC power at for example 350 - 400 V DC. The DC output of this first converter is connected to a DC input of a second converter 202. The second converter 202 is provided to convert de DC power to AC power of for example 230 V AC RMS, which is then fed to the critical load 204. The path formed by the first and the second converters is used when power needs to be fed from the AC power supply 205. The power processor unit 200 is further provided to receive power from a DC power supply 206 such as a battery providing a DC power at for example 48 V DC. Since the DC input of the second converter usually has a considerably higher voltage, the power processor unit 200 will also comprise a third converter 203 comprising a DC input provided to be connected to the DC power supply 206 and a DC output. The third converter 203 is preferably an isolated converter (as represented by the double diagonal line), but could in some application be non isolated. According to the invention and as illustrated in Figure 2, i this DC output is connected to both the DC output from the first converter 201 and the DC input from the second converter. The path formed by the third and the second converters is thus used when power needs to be fed from the DC power supply 206. A capacitor 207 is provided between the output of the first > converter 201 and the input of the second converter 202 and acts an energy storage unit. A micro-controller or controller 208 is connected to each of the three converters 201, 202 and 203 to communicate commands to each of the converters. The micro-controller is further connected to communication output 209. ) Figure 3 shows in more detail the first and second converters 201 and 202 of the power processor according to this first embodiment of the present invention. The first converter 201 comprises a first and a third half-bridge circuit 301, 303, both connected between a first and a second DC voltage bus 311, 312. The first half-bridge circuit 301 comprises a first switch 301a connected between an AC input line 313, comprising a first inductance 313i, and the first DC voltage bus 311, and a second switch 301b connected between the AC input line 313 and the second DC voltage bus 312. The third half-bridge circuit 303 comprises a fifth switch 303a, connected between a neutral line 314 and the first DC voltage bus 311, and a sixth switch 303b, connected between the neutral line 314 and the second DC voltage bus 312. The second converter 202 comprises a second and a fourth half-bridge circuit 302,304, both also connected between the first and the second DC voltage bus 311, 312. The second half-bridge circuit 302 comprises a third switch 302a, connected between a first AC output line 315, comprising an inductance 315?, and the first DC voltage bus 311, and a fourth switch 302b, connected between the first AC output line 315 and the second DC voltage bus 312. The fourth half bridge circuit 304 comprises a seventh switch 304a, connected between a second AC output line 316 and the first DC voltage bus 311, and an eighth switch 304b, connected between the second AC output line 316 and the second DC voltage bus 312. The DC/DC converter 203 and the capacitor 207 are then connected to the first and second DC voltage busses 311, 312 between the first and second converters 201 and 202. To convert the cyclical, substantially sinusoidal voltage of the AC power supply into a continuous voltage between the first and second DC voltage busses 311, 312, and to convert said continuous voltage back into a cyclical voltage between the first and second AC output lines 315,316, the micro-controller 208 commands the switches of at least the first and second half-bridge circuits 301,302 using pulse width modulation (PWM). Pulse width modulation uses a square wave whose duty cycle is modulated resulting in the variation of the average value of the waveform. By switching voltage with the approximate duty cycle, the output will approximate a voltage at the appropriate level, as depicted in Fig. 4. The first and second inductances 313i, 315i and the capacitor 207 attenuate the switching noise. The duty cycle of the square waveform is much shorter than that of the sine wave of either the input or output AC voltages, typically in the order of magnitude of microseconds, e.g. 20 us vs. 20 ms for a typical 50 Hz AC voltage. When the first AC input line 313 is connected to a single-phase AC power supply, a variable, cyclical voltage VL,jn is established at the first AC input line 313 in the form of a substantially sinusoidal wave. This AC voltage VUn has a frequency fUn, and therefore a cycle length 1/fL,in> and an amplitude VL,inpeak- VL,inpeak can be, for example 325 V, corresponding to an RMS AC voltage VUIIRMS of 230 V, and fLiin can be, for example, 50 Hz. During the first half of each cycle of VUn> the controllers leave the fifth switch 303a open, while the sixth switch 303b is closed so as to connect the second DC voltage bus 312 to the neutral line 314 and the first half-bridge circuit 301 is pulse width modulated to convert the variable positive voltage at the first AC input line 313 into a continuous voltage +Vb at the first DC voltage bus 311. During the second half of each cycle of VL,jn, the controllers close the fifth switch 303a, while the sixth switch 303b is opened so as to connect the first DC voltage bus 311 to the neutral line 314, and the first half-bridge circuit 301 is pulse width modulated to convert the variable negative voltage at the first AC input line 313 into a continuous voltage -Vb at the second DC i voltage bus 312. As a result, a substantially continuous voltage difference 2Vb is generated between the first DC voltage bus 311 and the second DC voltage bus 312. The first inductance 313i filters the switching noise of the first and second switches 301 a, 301 b. In the second half-bridge circuit 302, the third switch 302a ) and the fourth switch 302b, respectively connecting the first DC voltage bus 311 and the second DC voltage bus 312 to the first AC output line 315, are pulse width modulated so as to generate a cyclical, close to sinusoidal voltage VL,0ut at the first AC output line, with a frequency fL,0ut, an amplitude VL,0UtPeak close to Vb and a phase displacement Acp with respect to Vyn- The second inductance 315i filters the switching noise of the third and fourth switches 302a, 302b. In this first embodiment of the power backup processor of the invention, as illustrated in Fig. 3, the seventh switch 304a is open during at least part of the first half of each cycle of VL,0Ut and closed during at least part the second half. Inversely, the eighth switch 304b is closed during at least part of the first half and opened during at least part of the second half. As a result, a counter-cyclical voltage VN,0Ut is generated at the second AC output line 315 . Fig. 5 illustrates a cycle of the output voltages VL,out, VNi0Ut and Vioad=(VNiOUt-V\|_,out)- During a period ti' of at least 95% of the first half-cycle, during which the seventh switch 304a is open and the eighth switch 304b closed, VN,0Ut is substantially constant and equal to -Vb. During a period t2' of at least 95% of the second half-cycle, during which the seventh switch 304a is closed and the eighth switch 304b open, is VN,out substantially constant and equal to +Vb. During the transition period tz between V and t2', this fourth half-bridge circuit 304 is preferably pulse-width modulated to ensure a smooth transition between -Vb and +Vb and vice versa. A similar transition period also takes place between t2' and ti'. Ideally, both the first and the second derivatives of VN,0Ut are continuous. Each one of the periods t-,' and t2' can be continuous or split ! in several segments of, respectively, the first or second half-cycles. They can also be centred around the peaks of VL,0ut. as depicted, or, on the contrary, advanced or delayed with respect to those peaks and have the same or different lengths. As VN,out is countercyclical to VUout, the output voltage > V\|0ad=(VN,out-VL,0ut) supplied to the critical load has nearly twice the amplitude of VN,0Ut, as depicted in Fig. 5. This allows a comparatively high output voltage V\|0ad with a comparatively moderate DC voltage difference 2Vb between the first DC voltage bus 311 and the second DC voltage bus 312 If VN,out is substantially square or trapezoidal, it is preferable to adapt the pulse width modulation of the second half-bridge circuit 302 so that VL,out has a corrected sinusoidal form that in combination with VNout results in a closer to sinusoidal V\|0ad=(VN,out-VL,out)> as illustrated in Fig. 5. Depending on the length of t-T and t2\ the slope of VN,0Ut between -Vb and +Vb will be more or less pronounced, leading to a more square or trapezoidal wave shape, as can be seen by comparing Fig. 5 and Fig. 6, corresponding to an alternative where each one of ti' and t2' correspond to less than 95 % but at least 75% of each half-cycle. Having such a substantially square or trapezoidal wave shape for VN,out would result in a distorted wave shape of V\|0ad if the second half-bridge circuit 302 was pulse-width modulated to produce a sinusoidal wave shape of Vi_,out- For this reason, the second half-bridge circuit 302 is commanded so that VLout follows a corrected sine wave, as depicted in Figs. 5 and 6, resulting in a substantially sinusoidal V\|0ad- While the fourth half-bridge circuit 304 could instead be pulse-width modulated during the whole cycle, so as to generate a sinusoidal VN,0Ut that would not distort VLout, this would be considerably less energy-efficient than pulse-width modulating only the second half-bridge circuit 302 for the whole cycle with a corrected wave shape instead. The shorter the transition periods between V and t2', the bigger the correction of the wave shape of VL,0Ut will have to be. On the other hand, shorter transition periods between tj' and t2' have the advantage of limiting the number of switchovers of the fourth half-bridge circuit 304, with the corresponding advantages in higher efficiency, lower radio interference generation, etc. It is particularly advantageous to command both the third and the fourth half-bridge circuits 303, 304 using this method. However, it is also possible to command just one of them in this manner. Figs. 7 and 8 illustrate a simplified second embodiment of the power backup processor of the invention. In this second embodiment, the second half-bridge circuit 302 is synchronised with the first half-bridge circuit 301, so that VL,0Ut has substantially, or even precisely, the same frequency and phase as VUn. Since the third half-bridge circuit 303 is controlled so that the neutral line 314 is connected to the second DC voltage bus 312 during the first half of the cycle of VL,jn and therefore, in this embodiment, also of VL,0Ut. and to the first DC voltage bus 311 during the second half of the same cycle, this allows to dispense with the fourth half-bridge circuit 304 of the first embodiment and to connect the second AC output line 316 directly to the neutral line 314 instead. However, in this embodiment a third impedance 314i has to be interposed between the neutral line 314 and the third half-bridge circuit 303 to filter the switching noise of the fifth and sixth switches 303a, 303b. As shown in Figure 7, this forms, with the capacitor 207, one AC/DC/AC converter 701. In this second embodiment, the third half-bridge circuit 303 is also controlled in the way depicted by Figures 5 or 6, wherein during a period ti of at least 95%, respectively at least 75% of the first half-cycle, \| during which the fifth switch 303a is open and the sixth switch 303b closed, VN,0Ut is substantially constant and equal to -Vb. During a period t2 of at least 95%, respectively at least 75% of the second half-cycle, during which the fifth switch 303a is closed and the sixth switch 303b open, VNi0Ut is substantially constant and equal to +Vb. During the transition period t3 between ti and t2, this third half-bridge circuit 304 is preferably pulse-width modulated to ensure a smooth transition between -Vb and +Vb and vice versa. Ideally, both the first and the second derivatives of VN.out are continuous. Each one of the periods ti and t2 can be continuous or split in several segments of, respectively, the first or second half-cycles. They can also be centred around the peaks of VL,0ut, as depicted, or, on the contrary, advanced or delayed with respect to those peaks and have the same or different lengths. As shown in Figures 3 and 8, protection means 305 are preferably provided in one of the first or second DC voltage busses 311, 312, upstream of the connection 210 or 211, respectively, to the DC power source 206 and of the capacitor 207. The protection means 305 consist in particular of a fuse and allow to use the DC power source 206 when the first half-bridge circuit 301 breaks and could possibly short-circuit the DC voltage at the capacitor 207. The DC/DC converter 203 in both the first and the second embodiments can be bi-directional, thus allowing to direct power from the DC voltage busses 311,312 back to the DC power source 206, for instance for recharging a battery being used as the DC power source 206. The first and second converters 201,202 of the first embodiment and the AC/DC/AC converter 701 of the second embodiment can also be power bi-directional, allowing the recuperation of energy from the critical load 204 and/or the DC power source 206. For this purpose, the switches of the half-bridge circuits forming these first and second converters will have to be power bi-directional themselves, and the series of controllers 208 will have to be provided to run these converters 201 and/or 202 or 203 also in reverse. The switches of the half-bridge circuits can in particular be IGBT switches with antiparallel diodes. Figure 9 shows an embodiment from the processor according to the present invention comprising a plurality of processor units 200a, 200b, ... 200i connected in parallel. Each of the processor units 200a, 200b, ... 200i has a configuration as shown in Figures 2 or 7. A communication bus 300 connects the communication outputs 209 of the processor units. Hence the micro-controllers of the processor units are interconnected to allow synchronisation of the first AC outputs and to organise load sharing between the units. The principles of synchronisation and load sharing between units are known to the person skilled in the art and thus do not need to be described in detail. Preferably, as illustrated in Figure 9, the communication bus comprises a double connection between the units to provided redundancy in case one of the connections would fail. Instead of a cable connection, wireless connection using IR or HF technology, in particular Bluetooth technology, is also conceivable. It is also conceivable to provide one connection with cables and the other connection as a wireless connection. As will be appreciated, modifications are conceivable without falling outside the scope of the appended claims. For example, it is conceivable, instead of providing one micro-controller for each processor unit as illustrated in Figure 2, one micro-controller for each converter 201, 202 and 203 with communication means between each of the controllers. Having only one controller per processor unit is however advantageous, since it does not require means to ensure proper communication between the controllers of a same processor unit. As can be seen in the drawings, it is important that the three converters converge in one point: a DC bus bar at the capacitor 207. CLAIMS 1. A power backup processor unit (200) comprising: a) a first AC input line (313) comprising a first inductance (313i) and provided to be connected to an AC power supply, with a cyclical voltage VUn; b) a first AC output line (315) comprising a second inductance (315i) and provided to be connected to a critical load (204); c) a second AC output line (316) provided to be connected to the critical load (204); d) a neutral line (314) provided to be connected to a neutral port; e) first and second DC voltage busses (311,312) provided to be connected to a DC power supply (206); f) a capacitor (207) interposed between the first and second DC voltage busses (311,312); g) a first half-bridge circuit (301) comprising a first switch (301a) and a second switch (301b), wherein the first switch (301a) is connected between the first AC input line (313) and the first DC voltage bus (311) and the second switch (301b) is connected between the first AC input line (313) and the second DC voltage bus (312); h) a second half-bridge circuit (302) comprising a third switch (302a) and a fourth switch (302b), wherein the third switch (302a) is connected between the first AC output line (315) and the first DC voltage bus (311) and the fourth switch (302b) is connected between the first AC output line (315) and the second DC voltage bus (312); i) a third half-bridge circuit (303) comprising a fifth switch (303a) and a sixth switch (303b), wherein the fifth switch (303a) is connected between the neutral line (314) and the first DC voltage bus (311) and the sixth switch (303b) is connected between the neutral line (314) and the second DC voltage bus (312); a series of controllers (208) provided to command the switches (301a...303b), wherein said series of controllers (208) is provided to command at least the first to fourth switches (301 a...302b) using pulse width modulation to convert VL,in into two different, substantially continuous voltages +Vb,-Vb at the first and the second DC voltage busses (311,312) and said two different, substantially continuous voltages +Vb,-VD into a cyclical voltage VLi0ut at the first AC output line (315); and characterised in that it also comprises k) a fourth half-bridge circuit (304) comprising a seventh switch (304a) and an eighth switch (304b), wherein the seventh switch (304a) is connected between the first DC voltage bus (311) and the second AC output line (316) and the eighth switch (304b) is connected between the second DC voltage bus (312) and the second AC output line (316); and in that said series of controllers (208) is also provided to open the fifth switch (303a) and close the sixth switch (303b) for a period ti of at least 50%, and preferably at least 95%, of a first half of a cycle of VUn and close the fifth switch (303a) and open the sixth switch (303b) for a period t2 of at least 50%, and preferably at least 95%, of a second half of said cycle of VUn- 2. A power backup processor unit (200) according to claim 1, characterized in that said series of controllers (208) is also provided to open the seventh switch (304a) and close the eighth switch (304b) for a i period V of at least 50%, and preferably at least 95%, of a first half of a cycle of VL,out and close the seventh switch (304a) and open the eighth switch (304b) for a period t2' of at least 50%, and preferably at least 95% of a second half of said cycle of VL,0ut- 3. A power backup processor unit (200) according to claim ) 2, characterized in that said series of controllers (208) is also provided to pulse-width modulate said fourth half-bridge circuit (304) during a transition period t3' between V and t2'. 4. A power backup processor unit (200) according to one of claims 1 to 3, characterised in that the third, fourth, seventh and eighth switches (302a,302b,304a,304b) are power bi-directional, and the series of controllers is provided to run the second half-bridge circuit (302) in reverse, so as to convert an AC voltage between the first and second AC output lines (315,316) into a DC voltage between the two DC voltage busses (311,312). 5. A power backup processor unit (200) comprising: a) a first AC input line (313) comprising a first inductance (313i) and provided to be connected to an AC power supply with a cyclical voltage VUn; b) a first AC output line (315) comprising a second inductance (315i) and provided to be connected to a critical load (204); c) a second AC output line (316) provided to be connected to the critical load (204); d) a neutral line (314) provided to be connected to a neutral port; e) first and second DC voltage busses (311,312) provided to be connected to a DC power supply (206); f) a capacitor (207) interposed between the first and second DC voltage busses (311,312); g) a first half-bridge circuit (301) comprising a first switch (301a) and a second switch (301b), wherein the first switch (301a) is connected between the first AC input line (313) and the first DC voltage bus (311) and the second switch (301b) is connected between the first AC input line (313) and the second DC voltage bus (312); h) a second half-bridge circuit (302) comprising a third switch (302a) and a fourth switch (302b), wherein the third switch (302a) is connected between the first AC output line (315) and the first DC voltage bus (311) and the fourth switch (302b) is connected between the first AC output line (315) and the second DC voltage bus (312); i) a third half-bridge circuit (303) comprising a fifth switch (303a) and a sixth switch (303b), wherein the fifth switch (303a) is connected between the neutral line (314) and the first DC voltage bus (311) and the sixth switch (303b) is connected between the neutral line (314) and the second DC voltage bus (312); j) a series of controllers (208) provided to command the switches (301a...303b), wherein said series of controllers (208) is provided to command at least the first to fourth switches (301 a...302b) using pulse width modulation to convert VLiin into two different, substantially continuous voltages +Vb,-Vb at the first and the second DC voltage busses (311,312) and said two different, substantially continuous voltages +Vb,-Vb into a cyclical voltage VL>0ut at the first AC output line (315); and characterised in that it also comprises k) a third inductance (314i) connected between said neutral line (314) and said fifth and sixth switches (303a,303b); in that said second AC output line (316) is directly connected to said neutral line (314); in that said series of controllers (208) are provided to synchronize said first and second half-bridge circuits (301,302) so that VL,jn and VL,0ut have substantially the same phase and frequency, and in that said series of controllers (208) is also provided to open the fifth switch (303a) and close the sixth switch (303b) for a period ti of at least 50%, and preferably at least 95%, of a first half of a cycle of VL,m and close the fifth switch (303a) and open the sixth switch (303b) for a period t2 of at least 50%, and preferably at least 95%, of a second half of the cycle of VLin. 6. A power backup processor unit (200) according to claim 5, characterized in that said series of controllers (208) is also provided to pulse-width modulate said fifth switch (303a) and said sixth switch (303b) during a transition period t3 between ti and t2. 7. A power backup processor unit (200) according to one of claims 5 or 6, wherein the third and fourth switches (302a,302b) are bi¬directional, and the series of controllers (208) is also provided to run the second half-bridge circuit (302) in reverse, so as to convert an AC voltage between the first and second AC output lines (315,316) into a DC voltage between the two DC voltage busses (311,312). 8. A power backup processor unit (200) according to any one of the preceding claims, wherein the series of controllers (208) consists of one controller unit. 9. A power backup processor unit (200) according to one of the preceding claims, further comprising a DC/DC converter (203) connected to the first and second DC voltage busses (311,312) for connecting said first and second DC voltage busses (311,312) to said DC power source (206). 10.A power backup processor unit (200) according to claim 9, wherein the DC/DC converter (203) is bi-directional. 11. A power backup processor unit (200) according to one of the previous claims, wherein the first, second, fifth and sixth switches (301a,301b,303a,303b) are bi-directional and the series of controllers is provided to run the first half-bridge circuit (301) in reverse, so as to convert a DC voltage between the two DC voltage busses (311,312) into an AC voltage at the first AC input line (313). 12.A power backup processor system comprising a plurality of power backup processor units (200a...200i) as claimed in any one of the preceding claims and connected in parallel. 13. The power backup processor system according to claim 12, further comprising communication means, in particular at least one inter unit communication bus (300), connected to the controllers of each power backup processor unit (200a...200i). 14. A method of controlling a power backup processor unit (200), said power backup processor unit (200) comprising: a) a first AC input line (313) comprising a first inductance (313i) and provided to be connected to an AC power supply with a cyclical voltage VL,in; b) a first AC output line (315) comprising a second inductance (315i) and provided to be connected to a critical load (204); c) a second AC output line (316) provided to be connected to the critical load (204); d) a neutral line (314) provided to be connected to a neutral port; e) first and second DC voltage busses (311,312) provided to be connected to a DC power supply (206); f) a capacitor (207) interposed between the first and second DC voltage busses (311,312); g) a first half-bridge circuit (301) comprising a first switch (301a) and a second switch (301b), wherein the first switch (301a) is connected between the first AC input line (313) and the first DC voltage bus (311) and the second switch (301b) is connected between the first AC input line (313) and the second DC voltage bus (312); h) a second half-bridge circuit (302) comprising a third switch (302a) and a fourth switch (302b), wherein the third switch (302a) is connected between the first AC output line (315) and the first DC voltage bus (311) and the fourth switch (302b) is connected between the first AC output line (315) and the second DC voltage bus (312); i) a third half-bridge circuit (303) comprising a fifth switch (303a) and a sixth switch (303b), wherein the fifth switch (303a) is connected between the neutral line (314) and the first DC voltage bus (311) and the sixth switch (303b) is connected between the neutral line (314) and the second DC voltage bus (312); and wherein said method comprises the steps of: j) pulse width modulating said first half-bridge circuit (301) to convert VLlin into two different, substantially continuous voltages +Vb,-Vb at the first and the second DC voltage busses (311,312) and said second half-bridge circuit (302) to convert said two different, substantially continuous voltages +Vb,-Vb into a cyclical voltage VLi0Ut at the first AC output line (315); and is characterised in that it also comprises the steps of k) opening the fifth switch (303a) and closing the sixth switch (303b) for a period ti of at least 50%, and preferably at least 95%, of a first half of a cycle of VUn; and I) closing the fifth switch (303a) and opening the sixth switch (303b) for a period t2 of at least 50%, and preferably at least 95%, of a second half of the cycle of VUn. 15. A method according to claim 11 and characterized in that it also comprises the step of pulse-width modulating said fifth switch (303a) and said sixth switch (303b) during a transition period t3 between t1 and t2. 16. A method according to claims 11 or 12 and characterized in that the first and second half-bridge circuits (301,302) are synchronised so that VUn and VL,0Ut have substantially the same phase and frequency. 17. A method according to claim 13, wherein said second AC output line (316) is directly connected to the neutral line (314) and said power backup processor unit also comprises a third inductance (314i) connected between said neutral line (314) and said fifth and sixth switches (303a,303b). 18. A method according to one of claims 11-13 and characterized in that said power backup processor unit (200) further comprises: a) a fourth half-bridge circuit (304) comprising a seventh switch (304a) and an eighth switch (304b), wherein the seventh switch (304a) is connected between the first DC voltage bus (311) and the second AC output line (316) and the eighth switch (304b) is connected between the second DC voltage bus (312) and the second AC output line (316); and in that the method also comprises the steps of: b) opening the seventh switch (304a) and closing the eighth switch (304b) for a period ti' of at least 50%, and preferably at least 95%, of a first half of a cycle of VL,0Ut; and c) closing the seventh switch (304a) and closing the eighth switch (304b for a period t2' of at least 50%, and preferably at least 95%, of a second half of the cycle of VL,0Ut- 19. A method according to claim 14 and characterized in that it also comprises the step of pulse-width modulating said seventh switch (304a) and said fourth switch (304b) during a transition period t3' between V and t2'.

Full Text

"Power backup processor"
The present invention relates to a power backup processor unit comprising a first AC input line comprising a first inductance and provided to be connected to an AC power supply, a first AC output line comprising a second inductance and provided to be connected to a critical load, a second AC output line provided to be connected to the critical load, a neutral line provided to be connected to a neutral port, first and second DC voltage busses provided to be connected to a DC power supply, a capacitor interposed between the first and second DC voltage busses, a first half-bridge circuit comprising first and second switches, wherein the first switch is connected between the first AC input line and the first DC voltage bus and the second switch is connected between the first AC input line and the second DC voltage bus, a second half-bridge circuit comprising third and fourth switches, wherein the third switch is connected between the first AC output line and the first DC voltage bus and the fourth switch is connected between the first AC output line and the second DC voltage bus, a third half-bridge circuit comprising fifth and sixth switches, wherein the fifth switch is connected between the neutral line and the first DC voltage bus and the sixth switch
i is connected between the neutral line and the second DC voltage bus. The processor further comprises a series of controllers provided to command the switches, wherein said series of controllers is provided to command at least the first to fourth switches using pulse width modulation. The present invention also relates to a method of operating
said power backup processor.

Power backup processors are typically used in the telecommunication industry to ensure continuous delivery of AC energy to critical applications such as a central office of a telecommunication operator.
A configuration typically known from the state of the art and comprising a series of converters is illustrated in Figure 1. In this configuration, a first converter 101, which is an AC/DC converter, has a first AC input and a first DC output. The first AC input comprises a first AC input line 119 and a neutral line 120. Said first AC input line 119 is provided to be connected to a single-phase AC power supply, whereas said neutral line 120 is provided to be connected to a neutral port. A second converter 102, which is a DC/AC converter, has a first DC input and a first AC output, which comprises a first AC output line 121 and a second neutral line 122. Said first AC output line 121 is provided to be connected to a critical load 108, whereas said second neutral line 122 is provided to be connected to a neutral. A third converter 103, which is a DC/DC converter, has a second DC input and a second DC output, said second DC input being provided to be connected to a DC power supply. A fourth converter 104, which is another DC/DC converter, has a third DC input and a third DC output. The first DC output is connected to the third DC input, the third DC output to the second DC input and the second DC output to the first DC input.
The second converter 102 connected to the third converter 103 form together an inverter 100b, and the first converter 101 connected to the fourth converter 104 form together a rectifier 100a. A battery 106 is typically used as a DC power supply and therefore connected between the output from the rectifier 100a and the input from the inverter 100b. A switching unit 105 comprising switches 105a and 105b and a micro-controller 105c to control the switches is foreseen to i allow to switch between a connection using the power processor formed by the rectifier 100a and inverter 100b and a connection through the

cable 107. The critical load 108 is here illustrated by one resistance. In practise, the critical load may be formed by a plurality of units connected in parallel to the processor.
A problem with this known configuration as illustrated in Figure 1 is that the efficiency is relatively low. From the single-phase AC power supply to the critical load, the current needs to pass through four converters and one switch. The efficiency obtained through such a circuit is typically around 80%. When the critical load is fed with the DC power supply, the current needs to pass through two converters and one switch yielding an efficiency in the order of 90%.
United States Patent 4,709,318 discloses an alternative configuration which comprises just three converters, these three converters being a first converter, which is an AC/DC converter with a first AC input and a first DC output, a second converter, which is a DC/AC converter with a first DC input and a first AC output, and a third converter, which is a DC/DC converter provided with a second DC input and a second DC output. In this alternative configuration of the state of the art, the first AC input is provided to be connected to an AC power source, the first AC output is provided to be connected to a critical load, the second DC input is provided to be connected to a DC power source and both the first and second DC outputs are connected to two DC voltage busses in turn connected to the first DC input. With this configuration, the current only needs to pass through two converters between the AC power supply and the critical load. However, in this disclosure the first and second converters are such that the voltage between the DC voltage busses is comparatively high, namely 400 V DC to achieve a 120 V RMS AC output voltage. Such high voltage requires dimensioning the elements of the converters accordingly, increasing the cost while reducing both efficiency and reliability.
United States Patent Application Publication US 2005/0162137 A1 discloses a power backup processor comprising the

features of the preambles of the independent claims. In particular, this power backup processor comprises three AC phase input lines, each comprising an inductance and provided to be connected to a three-phase AC power supply, three AC phase output lines, each comprising another inductance and provided to be connected to a critical load, a first neutral line, first and second DC voltage busses provided to be connected to a DC power supply, a capacitor interposed between the first and second DC voltage busses, and a half-bridge circuit for each one of the three AC phase input lines, three AC phase output lines and first neutral line. Each half-bridge circuit comprises a switch connected between the corresponding AC phase input, AG phase output or neutral line and the first DC voltage bus and another switch connected between the same corresponding AC phase input, AC phase output or neutral line and the second DC voltage bus. This configuration also comprises a series of controllers provided to command all switches using pulse width modulation. In operation, the half-bridge circuits corresponding to the three AC phase input lines are commanded using pulse width modulation so as to generate, from the three-phase AC input, a nearly continuous positive voltage at the first DC voltage bus and a nearly continuous
i negative voltage at the second DC voltage bus. The half-bridge circuit corresponding to the first neutral line is commanded merely to compensate minor voltage fluctuations at the first and second DC voltage busses, both switches of this half-bridge being closed only for a very small percentage of the time and in very short pulses. The first neutral
5 line in this configuration therefore operates merely as a "0" volts axis. The normal object of this device is the zero sequence generation to reduce harmonic voltages on a three-phase output. These configuration and control method, apart from being suitable only for three-phase AC power supplies, furthermore also require a comparatively high DC
) voltage between the first and second DC voltage busses, namely up to 862 V DC for an output line-to-neutral voltage of 277 V.

It is a primary object of the present invention to provide a power backup processor and a method of operating said power backup processor suitable for a single-phase AC power supply and with a higher efficiency, at least when the critical load is fed with the single-phase AC power supply, while having a high availability and quality of voltage supply, and avoiding the drawbacks related to high DC voltages.
To this end, the power backup processor unit further comprises a fourth half-bridge circuit comprising seventh and eighth switches, wherein the seventh switch is connected between the second AC output line and the first DC voltage bus and the eighth switch is connected between the second AC output line and the second DC voltage bus, the series of controllers being provided to open the fifth switch and close the sixth switch for a period t1 of at least 50%, and preferably at least 95%, of a first half of a cycle of Vl in and close the fifth switch and open the sixth switch for a period t2 of at least 50%, and preferably at least 95%, of a second half of said cycle of VL,in- Preferably, said series of controllers is also provided to open the seventh switch and close the eighth switch for a period V of at least 50%, and preferably at least 95%, of a first half of a cycle of VL,0Ut and close the third switch and open the fourth switch for a period t2' of at least 50%, and preferably at least 95% of a second half of said cycle of VLout. This arrangement generates a voltage VN,out at the second AC output line that runs countercyclical^ to VL,0Ut. As a result, the voltage VLoad between the two connections to the load has an amplitude that is the sum of those of VLout and VNf0ut- An efficiency in the order of 90% can be obtained with the AC power supply. In addition, this circuitry has fewer components and is hence simplified when comparing it with prior art circuitries. A further consequence is that it allows having simultaneously a sinusoidal input current (without harmonics) while having a non linear critical load at the i output supplied by a sinusoidal voltage with a non sinusoidal current (with current harmonics). This insures proper harmonic filtering of the AC input

voltage and simultaneously the AC output current. It further allows proper functioning when a small phase shift between input (AC power supply) and output (at the critical load) is present as well as in case small voltage differences between input and output occur.
Alternatively, the neutral line is provided to be directly connected to the second AC output line, and the power backup processor further comprises a third inductance connected between the neutral line and the third half-bridge circuit, the series of controllers being provided to open the fifth switch and close the sixth switch for a period ti of at least 50%, and preferably at least 95%, of a first half of a cycle of VLiin and close the fifth switch and open the sixth switch for a period t2 of at least 50%, and preferably at least 95%, of a second half of said cycle of VL,jrv This second embodiment also generates a VN,0Ut that is countercyclical to VL,out- While in this simpler arrangement it is not possible to change the frequency and phase displacement of VL,0Ut with respect to VLin, the reduction in the number of components further increases the reliability, as well as the efficiency, which can reach around 95%.
Advantageously, the fifth and sixth switches and/or the seventh and eight switches are pulse-width moderated during a period t3, respectively t3', between U and t2, respectively V and t2\ so that VN,0Ut presents a continuity of at least its first and second derivates. This improves the longevity of the components and the cleanliness of the output.
i Preferably, the series of controllers consists of one
controller unit. As opposed to individual controllers for each converter, this allows managing more efficiently and easily the energy flow, without the need of adding additional components to manage communication between individual controllers.
) Preferably, the power backup processor unit further
comprises a DC/DC converter connected to the first and second DC

voltage busses for connecting said first and second DC voltage busses to said DC power source. This allows the use of a DC power source with a different, usually lower, voltage than the voltage between the two DC voltage busses.
In a particular embodiment, the DC/DC converter is bi directional. This makes it possible to use the device according to the invention as a rectifier, wherein current would flow from the AC input to the DC power source for recharging.
Advantageously, the first, second, fifth and sixth switches are power bi-directional and the series of controllers is provided to run the first half-bridge circuit in reverse, so as to convert a DC voltage between the two DC voltage busses into an AC voltage at the first AC input line. This allows using the device according to the invention as a means to supply energy from the DC power input into the AC power supply. A current flow in this direction could be applied for example in photovoltaic cell applications, wherein the energy generated by the cells is fed back to the AC power supply when not used by the critical load.
It can further be advantageous if the third, fourth and, if provided, the seventh and eighth switches are power bi-directional, and the series of controllers is also provided to run the second half-bridge circuit in reverse, so as to convert an AC voltage between the first and second AC output lines into a DC voltage between the two DC voltage busses. This allows the recuperation of energy from the critical load back into the AC and/or DC power supply, which principle could be applied to elevator systems.
Preferably, the power backup processor according to the invention comprises a plurality of power backup processor units connected in parallel, each power backup processor unit comprising the first, second and third converters as claimed in any one of the preceding claims. This allows to guarantee continuous operation should one of the

units fail to operate and without the presence of a single point or failure element such as switch 105a in the prior art device of Figure 1.
The device according to particular embodiments of the invention allows to suppress the following two negative effects occurring simultaneously and present in the prior art devices as illustrated in Figure 1. First, when power is supplied through switch 105b and cable 107, disturbances can occur by supplying power to the critical load without filtering. Secondly, when a critical non linear load is supplied, harmonic currents are generated on the AC power supply. This can lead to deterioration of the quality of the AC power supply voltage caused by harmonic currents which are applied to the AC power supply.
Other details and advantages will appear from the description of the annexed drawings.
Figure 1 illustrates a typical configuration of a power backup processor according to the prior art.
Figure 2 illustrates a first embodiment of the power backup processor unit according to the invention.
Figure 3 illustrates part of said first embodiment of the power backup processor unit according to the invention.
Figure 4 illustrates voltage conversion using pulse width modulation.
Figure 5 illustrates an example of the output voltages of the power backup processor unit according to the invention.
Figure 6 illustrates another example of the output voltages of the power backup processor unit according to the invention.
Figure 7 illustrates a second embodiment of the power backup processor according to the invention.
Figure 8 illustrates part of said second embodiment of the power backup processor according to the invention.
Figure 9 illustrates a further embodiment of the power backup processor according to the invention with several units in parallel.

In a first embodiment of the invention, as illustrated in Figure 2, a power processor unit 200 comprises a first converter 201 comprising an AC input connected to an AC power supply 205. This converter is provided to convert AC power at for example 230 V AC RMS to a DC power at for example 350 - 400 V DC. The DC output of this first converter is connected to a DC input of a second converter 202. The second converter 202 is provided to convert de DC power to AC power of for example 230 V AC RMS, which is then fed to the critical load 204. The path formed by the first and the second converters is used when power needs to be fed from the AC power supply 205.
The power processor unit 200 is further provided to receive power from a DC power supply 206 such as a battery providing a DC power at for example 48 V DC. Since the DC input of the second converter usually has a considerably higher voltage, the power processor unit 200 will also comprise a third converter 203 comprising a DC input provided to be connected to the DC power supply 206 and a DC output. The third converter 203 is preferably an isolated converter (as represented by the double diagonal line), but could in some application be non isolated. According to the invention and as illustrated in Figure 2, i this DC output is connected to both the DC output from the first converter 201 and the DC input from the second converter. The path formed by the third and the second converters is thus used when power needs to be fed from the DC power supply 206.
A capacitor 207 is provided between the output of the first
> converter 201 and the input of the second converter 202 and acts an
energy storage unit. A micro-controller or controller 208 is connected to
each of the three converters 201, 202 and 203 to communicate
commands to each of the converters. The micro-controller is further
connected to communication output 209.
) Figure 3 shows in more detail the first and second
converters 201 and 202 of the power processor according to this first

embodiment of the present invention. The first converter 201 comprises a first and a third half-bridge circuit 301, 303, both connected between a first and a second DC voltage bus 311, 312. The first half-bridge circuit 301 comprises a first switch 301a connected between an AC input line 313, comprising a first inductance 313i, and the first DC voltage bus 311, and a second switch 301b connected between the AC input line 313 and the second DC voltage bus 312. The third half-bridge circuit 303 comprises a fifth switch 303a, connected between a neutral line 314 and the first DC voltage bus 311, and a sixth switch 303b, connected between the neutral line 314 and the second DC voltage bus 312. The second converter 202 comprises a second and a fourth half-bridge circuit 302,304, both also connected between the first and the second DC voltage bus 311, 312. The second half-bridge circuit 302 comprises a third switch 302a, connected between a first AC output line 315, comprising an inductance 315?, and the first DC voltage bus 311, and a fourth switch 302b, connected between the first AC output line 315 and the second DC voltage bus 312. The fourth half bridge circuit 304 comprises a seventh switch 304a, connected between a second AC output line 316 and the first DC voltage bus 311, and an eighth switch 304b, connected between the second AC output line 316 and the second DC voltage bus 312. The DC/DC converter 203 and the capacitor 207 are then connected to the first and second DC voltage busses 311, 312 between the first and second converters 201 and 202.
To convert the cyclical, substantially sinusoidal voltage of the AC power supply into a continuous voltage between the first and second DC voltage busses 311, 312, and to convert said continuous voltage back into a cyclical voltage between the first and second AC output lines 315,316, the micro-controller 208 commands the switches of at least the first and second half-bridge circuits 301,302 using pulse width modulation (PWM). Pulse width modulation uses a square wave whose duty cycle is modulated resulting in the variation of the average value of

the waveform. By switching voltage with the approximate duty cycle, the output will approximate a voltage at the appropriate level, as depicted in Fig. 4. The first and second inductances 313i, 315i and the capacitor 207 attenuate the switching noise. The duty cycle of the square waveform is much shorter than that of the sine wave of either the input or output AC voltages, typically in the order of magnitude of microseconds, e.g. 20 us vs. 20 ms for a typical 50 Hz AC voltage.
When the first AC input line 313 is connected to a single-phase AC power supply, a variable, cyclical voltage VL,jn is established at the first AC input line 313 in the form of a substantially sinusoidal wave. This AC voltage VUn has a frequency fUn, and therefore a cycle length 1/fL,in> and an amplitude VL,inpeak- VL,inpeak can be, for example 325 V, corresponding to an RMS AC voltage VUIIRMS of 230 V, and fLiin can be, for example, 50 Hz. During the first half of each cycle of VUn> the controllers leave the fifth switch 303a open, while the sixth switch 303b is closed so as to connect the second DC voltage bus 312 to the neutral line 314 and the first half-bridge circuit 301 is pulse width modulated to convert the variable positive voltage at the first AC input line 313 into a continuous voltage +Vb at the first DC voltage bus 311. During the second half of each cycle of VL,jn, the controllers close the fifth switch 303a, while the sixth switch 303b is opened so as to connect the first DC voltage bus 311 to the neutral line 314, and the first half-bridge circuit 301 is pulse width modulated to convert the variable negative voltage at the first AC input line 313 into a continuous voltage -Vb at the second DC
i voltage bus 312. As a result, a substantially continuous voltage difference 2Vb is generated between the first DC voltage bus 311 and the second DC voltage bus 312. The first inductance 313i filters the switching noise of the first and second switches 301 a, 301 b.
In the second half-bridge circuit 302, the third switch 302a
) and the fourth switch 302b, respectively connecting the first DC voltage bus 311 and the second DC voltage bus 312 to the first AC output line

315, are pulse width modulated so as to generate a cyclical, close to sinusoidal voltage VL,0ut at the first AC output line, with a frequency fL,0ut, an amplitude VL,0UtPeak close to Vb and a phase displacement Acp with respect to Vyn- The second inductance 315i filters the switching noise of the third and fourth switches 302a, 302b.
In this first embodiment of the power backup processor of the invention, as illustrated in Fig. 3, the seventh switch 304a is open during at least part of the first half of each cycle of VL,0Ut and closed during at least part the second half. Inversely, the eighth switch 304b is closed during at least part of the first half and opened during at least part of the second half. As a result, a counter-cyclical voltage VN,0Ut is generated at the second AC output line 315 .
Fig. 5 illustrates a cycle of the output voltages VL,out, VNi0Ut and Vioad=(VNiOUt-V|_,out)- During a period ti' of at least 95% of the first half-cycle, during which the seventh switch 304a is open and the eighth switch 304b closed, VN,0Ut is substantially constant and equal to -Vb. During a period t2' of at least 95% of the second half-cycle, during which the seventh switch 304a is closed and the eighth switch 304b open, is VN,out substantially constant and equal to +Vb. During the transition period tz between V and t2', this fourth half-bridge circuit 304 is preferably pulse-width modulated to ensure a smooth transition between -Vb and +Vb and vice versa. A similar transition period also takes place between t2' and ti'. Ideally, both the first and the second derivatives of VN,0Ut are continuous. Each one of the periods t-,' and t2' can be continuous or split ! in several segments of, respectively, the first or second half-cycles. They can also be centred around the peaks of VL,0ut. as depicted, or, on the contrary, advanced or delayed with respect to those peaks and have the same or different lengths.
As VN,out is countercyclical to VUout, the output voltage
> V|0ad=(VN,out-VL,0ut) supplied to the critical load has nearly twice the
amplitude of VN,0Ut, as depicted in Fig. 5. This allows a comparatively high

output voltage V|0ad with a comparatively moderate DC voltage difference 2Vb between the first DC voltage bus 311 and the second DC voltage bus 312 If VN,out is substantially square or trapezoidal, it is preferable to adapt the pulse width modulation of the second half-bridge circuit 302 so that VL,out has a corrected sinusoidal form that in combination with VNout results in a closer to sinusoidal V|0ad=(VN,out-VL,out)> as illustrated in Fig. 5.
Depending on the length of t-T and t2\ the slope of VN,0Ut between -Vb and +Vb will be more or less pronounced, leading to a more square or trapezoidal wave shape, as can be seen by comparing Fig. 5 and Fig. 6, corresponding to an alternative where each one of ti' and t2' correspond to less than 95 % but at least 75% of each half-cycle. Having such a substantially square or trapezoidal wave shape for VN,out would result in a distorted wave shape of V|0ad if the second half-bridge circuit 302 was pulse-width modulated to produce a sinusoidal wave shape of Vi_,out- For this reason, the second half-bridge circuit 302 is commanded so that VLout follows a corrected sine wave, as depicted in Figs. 5 and 6, resulting in a substantially sinusoidal V|0ad- While the fourth half-bridge circuit 304 could instead be pulse-width modulated during the whole cycle, so as to generate a sinusoidal VN,0Ut that would not distort VLout, this would be considerably less energy-efficient than pulse-width modulating only the second half-bridge circuit 302 for the whole cycle with a corrected wave shape instead. The shorter the transition periods between V and t2', the bigger the correction of the wave shape of VL,0Ut will have to be. On the other hand, shorter transition periods between tj' and t2' have the advantage of limiting the number of switchovers of the fourth half-bridge circuit 304, with the corresponding advantages in higher efficiency, lower radio interference generation, etc.
It is particularly advantageous to command both the third and the fourth half-bridge circuits 303, 304 using this method. However, it is also possible to command just one of them in this manner.

Figs. 7 and 8 illustrate a simplified second embodiment of the power backup processor of the invention. In this second embodiment, the second half-bridge circuit 302 is synchronised with the first half-bridge circuit 301, so that VL,0Ut has substantially, or even precisely, the same frequency and phase as VUn. Since the third half-bridge circuit 303 is controlled so that the neutral line 314 is connected to the second DC voltage bus 312 during the first half of the cycle of VL,jn and therefore, in this embodiment, also of VL,0Ut. and to the first DC voltage bus 311 during the second half of the same cycle, this allows to dispense with the fourth half-bridge circuit 304 of the first embodiment and to connect the second AC output line 316 directly to the neutral line 314 instead. However, in this embodiment a third impedance 314i has to be interposed between the neutral line 314 and the third half-bridge circuit 303 to filter the switching noise of the fifth and sixth switches 303a, 303b.
As shown in Figure 7, this forms, with the capacitor 207, one AC/DC/AC converter 701.
In this second embodiment, the third half-bridge circuit 303 is also controlled in the way depicted by Figures 5 or 6, wherein during a period ti of at least 95%, respectively at least 75% of the first half-cycle, | during which the fifth switch 303a is open and the sixth switch 303b closed, VN,0Ut is substantially constant and equal to -Vb. During a period t2 of at least 95%, respectively at least 75% of the second half-cycle, during which the fifth switch 303a is closed and the sixth switch 303b open, VNi0Ut is substantially constant and equal to +Vb. During the transition period t3 between ti and t2, this third half-bridge circuit 304 is preferably pulse-width modulated to ensure a smooth transition between -Vb and +Vb and vice versa. Ideally, both the first and the second derivatives of VN.out are continuous. Each one of the periods ti and t2 can be continuous or split in several segments of, respectively, the first or second half-cycles. They can also be centred around the peaks of VL,0ut,

as depicted, or, on the contrary, advanced or delayed with respect to those peaks and have the same or different lengths.
As shown in Figures 3 and 8, protection means 305 are preferably provided in one of the first or second DC voltage busses 311, 312, upstream of the connection 210 or 211, respectively, to the DC power source 206 and of the capacitor 207. The protection means 305 consist in particular of a fuse and allow to use the DC power source 206 when the first half-bridge circuit 301 breaks and could possibly short-circuit the DC voltage at the capacitor 207.
The DC/DC converter 203 in both the first and the second embodiments can be bi-directional, thus allowing to direct power from the DC voltage busses 311,312 back to the DC power source 206, for instance for recharging a battery being used as the DC power source 206.
The first and second converters 201,202 of the first embodiment and the AC/DC/AC converter 701 of the second embodiment can also be power bi-directional, allowing the recuperation of energy from the critical load 204 and/or the DC power source 206. For this purpose, the switches of the half-bridge circuits forming these first and second converters will have to be power bi-directional themselves, and the series of controllers 208 will have to be provided to run these converters 201 and/or 202 or 203 also in reverse. The switches of the half-bridge circuits can in particular be IGBT switches with antiparallel diodes.
Figure 9 shows an embodiment from the processor according to the present invention comprising a plurality of processor units 200a, 200b, ... 200i connected in parallel. Each of the processor units 200a, 200b, ... 200i has a configuration as shown in Figures 2 or 7. A communication bus 300 connects the communication outputs 209 of the processor units. Hence the micro-controllers of the processor units are interconnected to allow synchronisation of the first AC outputs and to

organise load sharing between the units. The principles of synchronisation and load sharing between units are known to the person skilled in the art and thus do not need to be described in detail. Preferably, as illustrated in Figure 9, the communication bus comprises a double connection between the units to provided redundancy in case one of the connections would fail. Instead of a cable connection, wireless connection using IR or HF technology, in particular Bluetooth technology, is also conceivable. It is also conceivable to provide one connection with cables and the other connection as a wireless connection.
As will be appreciated, modifications are conceivable without falling outside the scope of the appended claims. For example, it is conceivable, instead of providing one micro-controller for each processor unit as illustrated in Figure 2, one micro-controller for each converter 201, 202 and 203 with communication means between each of the controllers. Having only one controller per processor unit is however advantageous, since it does not require means to ensure proper communication between the controllers of a same processor unit. As can be seen in the drawings, it is important that the three converters converge in one point: a DC bus bar at the capacitor 207.

CLAIMS
1. A power backup processor unit (200) comprising:
a) a first AC input line (313) comprising a first inductance (313i) and provided to be connected to an AC power supply, with a cyclical voltage VUn;
b) a first AC output line (315) comprising a second inductance (315i) and provided to be connected to a critical load (204);
c) a second AC output line (316) provided to be connected to the critical load (204);
d) a neutral line (314) provided to be connected to a neutral port;
e) first and second DC voltage busses (311,312) provided to be connected to a DC power supply (206);
f) a capacitor (207) interposed between the first and second DC voltage busses (311,312);
g) a first half-bridge circuit (301) comprising a first switch (301a) and a second switch (301b), wherein the first switch (301a) is connected between the first AC input line (313) and the first DC voltage bus (311) and the second switch (301b) is connected between the first AC input line (313) and the second DC voltage bus (312);
h) a second half-bridge circuit (302) comprising a third switch (302a) and a fourth switch (302b), wherein the third switch (302a) is connected between the first AC output line (315) and the first DC voltage bus (311) and the fourth switch (302b) is connected between the first AC output line (315) and the second DC voltage bus (312);
i) a third half-bridge circuit (303) comprising a fifth switch (303a) and a
sixth switch (303b), wherein the fifth switch (303a) is connected
between the neutral line (314) and the first DC voltage bus (311)
and the sixth switch (303b) is connected between the neutral line
(314) and the second DC voltage bus (312);

a series of controllers (208) provided to command the switches (301a...303b), wherein said series of controllers (208) is provided to command at least the first to fourth switches (301 a...302b) using pulse width modulation to convert VL,in into two different, substantially continuous voltages +Vb,-Vb at the first and the second DC voltage busses (311,312) and said two different, substantially continuous voltages +Vb,-VD into a cyclical voltage VLi0ut at the first AC output line (315); and characterised in that it also comprises
k) a fourth half-bridge circuit (304) comprising a seventh switch (304a)
and an eighth switch (304b), wherein the seventh switch (304a) is
connected between the first DC voltage bus (311) and the second
AC output line (316) and the eighth switch (304b) is connected
between the second DC voltage bus (312) and the second AC
output line (316); and
in that said series of controllers (208) is also provided to open the fifth
switch (303a) and close the sixth switch (303b) for a period ti of at
least 50%, and preferably at least 95%, of a first half of a cycle of VUn
and close the fifth switch (303a) and open the sixth switch (303b) for a
period t2 of at least 50%, and preferably at least 95%, of a second half
of said cycle of VUn-
2. A power backup processor unit (200) according to claim
1, characterized in that said series of controllers (208) is also provided to
open the seventh switch (304a) and close the eighth switch (304b) for a
i period V of at least 50%, and preferably at least 95%, of a first half of a cycle of VL,out and close the seventh switch (304a) and open the eighth switch (304b) for a period t2' of at least 50%, and preferably at least 95% of a second half of said cycle of VL,0ut-
3. A power backup processor unit (200) according to claim
) 2, characterized in that said series of controllers (208) is also provided to

pulse-width modulate said fourth half-bridge circuit (304) during a transition period t3' between V and t2'.
4. A power backup processor unit (200) according to one of claims 1 to 3, characterised in that the third, fourth, seventh and eighth switches (302a,302b,304a,304b) are power bi-directional, and the series of controllers is provided to run the second half-bridge circuit (302) in reverse, so as to convert an AC voltage between the first and second AC output lines (315,316) into a DC voltage between the two DC voltage busses (311,312).
5. A power backup processor unit (200) comprising:

a) a first AC input line (313) comprising a first inductance (313i) and provided to be connected to an AC power supply with a cyclical voltage VUn;
b) a first AC output line (315) comprising a second inductance (315i) and provided to be connected to a critical load (204);
c) a second AC output line (316) provided to be connected to the critical load (204);
d) a neutral line (314) provided to be connected to a neutral port;
e) first and second DC voltage busses (311,312) provided to be connected to a DC power supply (206);
f) a capacitor (207) interposed between the first and second DC voltage busses (311,312);
g) a first half-bridge circuit (301) comprising a first switch (301a) and a second switch (301b), wherein the first switch (301a) is connected between the first AC input line (313) and the first DC voltage bus (311) and the second switch (301b) is connected between the first AC input line (313) and the second DC voltage bus (312);
h) a second half-bridge circuit (302) comprising a third switch (302a) and a fourth switch (302b), wherein the third switch (302a) is connected between the first AC output line (315) and the first DC voltage bus (311) and the fourth switch (302b) is connected

between the first AC output line (315) and the second DC voltage bus (312); i) a third half-bridge circuit (303) comprising a fifth switch (303a) and a sixth switch (303b), wherein the fifth switch (303a) is connected between the neutral line (314) and the first DC voltage bus (311) and the sixth switch (303b) is connected between the neutral line (314) and the second DC voltage bus (312); j) a series of controllers (208) provided to command the switches (301a...303b), wherein said series of controllers (208) is provided to command at least the first to fourth switches (301 a...302b) using pulse width modulation to convert VLiin into two different, substantially continuous voltages +Vb,-Vb at the first and the second DC voltage busses (311,312) and said two different, substantially continuous voltages +Vb,-Vb into a cyclical voltage VL>0ut at the first AC output line (315); and characterised in that it also comprises k) a third inductance (314i) connected between said neutral line (314)
and said fifth and sixth switches (303a,303b); in that said second AC output line (316) is directly connected to said neutral line (314);
in that said series of controllers (208) are provided to synchronize said
first and second half-bridge circuits (301,302) so that VL,jn and VL,0ut
have substantially the same phase and frequency, and
in that said series of controllers (208) is also provided to open the fifth
switch (303a) and close the sixth switch (303b) for a period ti of at
least 50%, and preferably at least 95%, of a first half of a cycle of VL,m
and close the fifth switch (303a) and open the sixth switch (303b) for a
period t2 of at least 50%, and preferably at least 95%, of a second half
of the cycle of VLin.
6. A power backup processor unit (200) according to claim
5, characterized in that said series of controllers (208) is also provided to

pulse-width modulate said fifth switch (303a) and said sixth switch (303b) during a transition period t3 between ti and t2.
7. A power backup processor unit (200) according to one of claims 5 or 6, wherein the third and fourth switches (302a,302b) are bi¬directional, and the series of controllers (208) is also provided to run the second half-bridge circuit (302) in reverse, so as to convert an AC voltage between the first and second AC output lines (315,316) into a DC voltage between the two DC voltage busses (311,312).
8. A power backup processor unit (200) according to any one of the preceding claims, wherein the series of controllers (208) consists of one controller unit.
9. A power backup processor unit (200) according to one of the preceding claims, further comprising a DC/DC converter (203) connected to the first and second DC voltage busses (311,312) for connecting said first and second DC voltage busses (311,312) to said DC power source (206).
10.A power backup processor unit (200) according to claim 9, wherein the DC/DC converter (203) is bi-directional.
11. A power backup processor unit (200) according to one of the previous claims, wherein the first, second, fifth and sixth switches (301a,301b,303a,303b) are bi-directional and the series of controllers is provided to run the first half-bridge circuit (301) in reverse, so as to convert a DC voltage between the two DC voltage busses (311,312) into an AC voltage at the first AC input line (313).
12.A power backup processor system comprising a plurality of power backup processor units (200a...200i) as claimed in any one of the preceding claims and connected in parallel.
13. The power backup processor system according to claim 12, further comprising communication means, in particular at least one inter unit communication bus (300), connected to the controllers of each power backup processor unit (200a...200i).

14. A method of controlling a power backup processor unit (200), said power backup processor unit (200) comprising:
a) a first AC input line (313) comprising a first inductance (313i) and provided to be connected to an AC power supply with a cyclical voltage VL,in;
b) a first AC output line (315) comprising a second inductance (315i) and provided to be connected to a critical load (204);
c) a second AC output line (316) provided to be connected to the critical load (204);
d) a neutral line (314) provided to be connected to a neutral port;
e) first and second DC voltage busses (311,312) provided to be connected to a DC power supply (206);
f) a capacitor (207) interposed between the first and second DC voltage busses (311,312);
g) a first half-bridge circuit (301) comprising a first switch (301a) and a second switch (301b), wherein the first switch (301a) is connected between the first AC input line (313) and the first DC voltage bus (311) and the second switch (301b) is connected between the first AC input line (313) and the second DC voltage bus (312);
h) a second half-bridge circuit (302) comprising a third switch (302a) and a fourth switch (302b), wherein the third switch (302a) is connected between the first AC output line (315) and the first DC voltage bus (311) and the fourth switch (302b) is connected between the first AC output line (315) and the second DC voltage bus (312);
i) a third half-bridge circuit (303) comprising a fifth switch (303a) and a sixth switch (303b), wherein the fifth switch (303a) is connected between the neutral line (314) and the first DC voltage bus (311) and the sixth switch (303b) is connected between the neutral line (314) and the second DC voltage bus (312); and
wherein said method comprises the steps of:

j) pulse width modulating said first half-bridge circuit (301) to convert VLlin into two different, substantially continuous voltages +Vb,-Vb at the first and the second DC voltage busses (311,312) and said second half-bridge circuit (302) to convert said two different, substantially continuous voltages +Vb,-Vb into a cyclical voltage VLi0Ut at the first AC output line (315);
and is characterised in that it also comprises the steps of
k) opening the fifth switch (303a) and closing the sixth switch (303b) for a period ti of at least 50%, and preferably at least 95%, of a first half of a cycle of VUn; and
I) closing the fifth switch (303a) and opening the sixth switch (303b) for a period t2 of at least 50%, and preferably at least 95%, of a second half of the cycle of VUn.
15. A method according to claim 11 and characterized in that it also comprises the step of pulse-width modulating said fifth switch (303a) and said sixth switch (303b) during a transition period t3 between t1 and t2.
16. A method according to claims 11 or 12 and characterized in that the first and second half-bridge circuits (301,302) are synchronised so that VUn and VL,0Ut have substantially the same phase and frequency.
17. A method according to claim 13, wherein said second AC output line (316) is directly connected to the neutral line (314) and said power backup processor unit also comprises a third inductance (314i) connected between said neutral line (314) and said fifth and sixth switches (303a,303b).
18. A method according to one of claims 11-13 and characterized in that said power backup processor unit (200) further comprises:
a) a fourth half-bridge circuit (304) comprising a seventh switch (304a) and an eighth switch (304b), wherein the seventh switch (304a) is

connected between the first DC voltage bus (311) and the second AC output line (316) and the eighth switch (304b) is connected between the second DC voltage bus (312) and the second AC output line (316); and in that the method also comprises the steps of:
b) opening the seventh switch (304a) and closing the eighth switch
(304b) for a period ti' of at least 50%, and preferably at least 95%,
of a first half of a cycle of VL,0Ut; and
c) closing the seventh switch (304a) and closing the eighth switch
(304b for a period t2' of at least 50%, and preferably at least 95%, of
a second half of the cycle of VL,0Ut-
19. A method according to claim 14 and characterized in that it also comprises the step of pulse-width modulating said seventh switch (304a) and said fourth switch (304b) during a transition period t3' between V and t2'.

Documents:

4075-CHENP-2008 AMENDED CLAIMS 24-03-2014.pdf

4075-CHENP-2008 CORRESPONDENCE OTHERS 16-04-2013.pdf

4075-CHENP-2008 CORRESPONDENCE OTHERS 24-03-2014.pdf

4075-CHENP-2008 FORM-3 24-03-2014.pdf

4075-CHENP-2008 OTHERS 22-10-2013.pdf

4075-CHENP-2008 AMENDED PAGES OF SPECIFICATION 22-10-2013.pdf

4075-CHENP-2008 AMENDED CLAIMS 22-10-2013.pdf

4075-CHENP-2008 CORRESPONDENCE OTHERS 05-03-2014.pdf

4075-CHENP-2008 EXAMINATION REPORT REPLY RECEIVED. 22-10-2013.pdf

4075-CHENP-2008 FORM-1 05-03-2014.pdf

4075-CHENP-2008 FORM-3 22-10-2013.pdf

4075-chenp-2008 abstract.pdf

4075-chenp-2008 claims.pdf

4075-chenp-2008 correspondence-others.pdf

4075-chenp-2008 description(complete).pdf

4075-chenp-2008 drawings.pdf

4075-chenp-2008 form-1.pdf

4075-chenp-2008 form-18.pdf

4075-chenp-2008 form-26.pdf

4075-chenp-2008 form-3.pdf

4075-chenp-2008 form-5.pdf

4075-chenp-2008 pct.pdf

4111-2008 Petition.pdf

« Previous Patent

Next Patent »

Patent Number

260511

Indian Patent Application Number

4075/CHENP/2008

PG Journal Number

19/2014

Publication Date

09-May-2014

Grant Date

02-May-2014

Date of Filing

04-Aug-2008

Name of Patentee

CONSTRUCTIONS ELECTRONIQUES + TELECOMMUNICATIONS

Applicant Address

RUE DU CHARBONNAGE, 18, B-4020 LIEGE (WANDRE)

Inventors:

#	Inventor's Name	Inventor's Address
1	BLEUS, PAUL	RUE A. PONSON 55, B-4020 JUPILLE

PCT International Classification Number

H02J9/00

PCT International Application Number

PCT/EP06/66237

PCT International Filing date

2006-09-11

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1	06100122.8	2006-01-05	EUROPEAN UNION